Sunday, 15 December 2019

Porting a design from IceStick to IceBreaker

My new IceBreaker is working fine and in principle it isn't that difficult to port my 8-bit SoC + Monitor to icebreaker but I encountered two issues:
  1. there is no SB_PLL40_CORE tile available for the fast clock.
    It seems there should be an almost equivalent SB_ICE40_PAD tile on the up5k but for now I just commented it out and use the 12Mhz clock everywhere
  2. there appear to be all sort of timing issues in the cpu,
    especially when reading from the ram and ram. The monitor didn't exhibit any issues until I started changing things in the state machine of the cpu. Now icetime doesn't report any issues but it still weird. This is of course my complete lack of experience with verilog and fpgas in general but thatÅ› of course the whole point of this exercise: finding out 'stuff' :-)
Because of this I am thinking about another approach and starting from scratch on the IceBreaker with a new CPU design. Again, bottom up but now hopefully with a more robust design that can be afforded because of the larger number of resources available.

Results will show up in

CPU design

The CPU design as currently implemented largely follows the diagram shown below. It features a 16 x 32bit register file and 16 bit instructi...