In the final design the FIFOs will be put into modules but in the next article an ad-hox design will be shown that allows us to test the basic principle.
Saturday 21 December 2019
Adding fifos to the UART
Because processing the incoming data on a serial line might cause a mismatch between speed of reception vs. the speed of transmission, it is a good idea to have buffers, also known as FIFOs, between the UART and the parts of the SoC that process the data. The design will look like the image below. The FIFOs will be implemented using the block rams available on the up5k. Each blockram can be configured as 512 bytes by 8 bit of data, which gives us plenty buffer space.
In the final design the FIFOs will be put into modules but in the next article an ad-hox design will be shown that allows us to test the basic principle.
In the final design the FIFOs will be put into modules but in the next article an ad-hox design will be shown that allows us to test the basic principle.
CPU design
The CPU design as currently implemented largely follows the diagram shown below. It features a 16 x 32bit register file and 16 bit instructi...